Eectiveness of Register Preloading on Cp-pacs Node Processor

CP-PACS is a massively parallel processor (MPP) for large scale scienti c computations. On September 1996, CP-PACS equipped with 2048 processors began its operation at University of Tsukuba. At that time, CP-PACS was the fastest MPP in the world on LINPACK benchmark. CP-PACS was designed to achieve very high performance in large scienti c/engineering applications. It is well known that ordinary data cache is not effective in such applications because data size is much larger than cache size and because there is little temporal locality. Thus, a special mechanism for hiding long memory access latency is indispensable. Cache prefetching is a well-known technique for this purpose. In addition to cache prefetching, CP-PACS node processors implement register preloading mechanism. This mechanism enables the processor to transfer required oating-point data directly (not via data cache) between main memory and oating-point registers in pipelined way. We compare register preloading with cache prefetching by measuring real performance of CP-PACS processor and HP PA-8000 processor which implement cache prefetching and/or register preloading. The results revealed the following points. First, register preloading outperforms cache prefetching in consecutive data access. This is because cache prefetching suffers from lack of memory/cache throughput. Second, superiority of register preloading to cache prefetching signi cantly increases in stride access. This is because cache prefetching transfers not only the required data but also unnecessary data in the cache line. This leads to the waste of memory/cache throughput. Third, register preloading is also e ective in indirectly indexed vector computations. Fourth, in multidimensional application, register preloading achieves stabler and better performance than cache-based computations even though blocking optimization is utilized in cache-based computations. From these results, it is concluded that register preloading is superior to cache prefetching for large numerical applications.